Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
User designs sometimes include one or more arithmetic operations where a first input is incremented and then multiplied by a second input. Conventional methods for synthesizing and/or mapping such incrementer-multiplier operations into configurable resources in a PLD can lead to a relatively large propagation delay, particularly for large numerical inputs, which in turn results in an increased clock period and reduced clock frequency for the PLD. Moreover, such conventional methods may also inefficiently allocate configurable resources and interconnections.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.